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ltc3859a 1 3859afa typical application description low i q , triple output, buck/buck/boost synchronous controller with improved burst mode operation the lt c ? 3859a is a high performance triple output (buck/ buck/boost) synchronous dc/dc switching regulator controller that drives all n-channel power mosfet stages. constant frequency current mode architecture allows a phase-lockable switching frequency of up to 850khz. the ltc3859 a operates from a wide 4.5v to 38v input supply range. when biased from the output of the boost converter or another auxiliary supply, the ltc3859 a can operate from an input supply as low as 2.5v after start-up. the 55a no-load quiescent current extends operating runtime in battery powered systems. opti-loop com - pensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the ltc3859 a features a precision 0.8v reference for the bucks, 1.2v reference for the boost and a power good output indicator. the pllin/mode pin selects among burst mode operation, pulse-skipping mode, or continu - ous inductor current mode at light loads.compared to the ltc3859 , the ltc3859 a's boost controller has improved performance in burst mode operation when the input voltage is higher than the regulated output voltage. l , lt, ltc, ltm, burst mode, opti-loop and module are registered trademarks and no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258. features applications n dual buck plus single boost synchronous controllers n outputs remain in regulation through cold crank down to 2.5v n low operating i q : 55a (one channel on) n wide bias input voltage range: 4.5v to 38v n buck output voltage range: 0.8v v out 24v n boost output voltage up to 60v n r sense or dcr current sensing n 100% duty cycle for boost synchronous mosfet even in burst mode ? operation n phase-lockable frequency (75khz to 850khz) n programmable fixed frequency (50khz to 900khz) n selectable continuous, pulse-skipping or low ripple burst mode operation at light loads n very low buck dropout operation: 99% duty cycle n adjustable output voltage soft-start or tracking n low shutdown i q : 14a n small 38-pin 5mm 7mm qfn and tssop packages n automotive always-on and start-stop systems n battery operated digital devices n distributed dc power systems n multioutput buck-boost applications efficiency vs input voltage 3859 ta01a ltc3859a v fb3 tg3 bg3 sense3 C sense3 + intv cc boost1, 2, 3i th1, 2, 3 track/ss1, 2ss3 sw1 sense1 + sense1 C v fb1 run1, 2, 3 extv cc tg2 sw2 bg2 sense2+sense2C v fb2 pgnd sgnd v bias 4.9h 6m 357k 220f 1f 68.1k 68.1k 649k 68f 68.1k 1.2h 2m 499k 4.7f sw1, 2, 3 0.1f 0.1f v in 2.5v to 38v (start-up above 5v) v out1 5v5a v out1 v out2 8.5v3a 220f 220f v out3 regulated at 10v when v in < 10v follows v in when v in > 10v 6.5h 8m tg1 sw3 bg1 input voltage (v) 0 efficiency (%) 100 9585 75 65 55 9080 70 60 50 20 10 30 3859a ta01b 40 15 35 5 25 figure 12 circuiti load = 2a v out2 = 8.5v v out1 = 5v downloaded from: http:///
ltc3859a 2 3859afa absolute maximum ratings bias input supply voltage (v bias ) .............. C 0.3v to 40v buck top side driver voltages (boost1, boost2) ............................. C 0.3v to 46v boost top side driver voltages (boost3) ............................................ C 0.3v to 76v buck switch voltage (sw1, sw2) ................ C 5v to 40v boost switch voltage (sw3) ........................ C 5v to 70v intv cc , (boost1C sw1), (boost2 Csw2), (boost3C sw3), .......... C 0.3v to 6v ru n1 , ru n2 , ru n3 .................................... C 0.3v to 8v maximum current sourced into pin from source > 8v .............................................. 100a (notes 1, 3) 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 top view fe package 38-lead plastic tssop 3837 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 i th1 v fb1 sense1 + sense1 C freq pllin/mode ss3 sense3 + sense3 C v fb3 i th3 sgnd run1run2 run3 sense2 C sense2 + v fb2 i th2 track/ss1pgood1 tg1 sw1 boost1 bg1 sw3 tg3 boost3 bg3 v bias extv cc intv cc bg2boost2 sw2 tg2 ov3 track/ss2 39 pgnd t jmax = 150c, q ja = 25c/w exposed pad (pin 39) is pgnd, must be soldered to pcb 13 14 15 16 top view 39 pgnd uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 freq pllin/mode ss3 sense3 + sense3 C v fb3 i th3 sgnd run1run2 run3 sense2 C sw1boost1 bg1 sw3 tg3 boost3 bg3 v bias extv cc intv cc bg2boost2 sense1 C sense1 + v fb1 i th1 track/ss1pgood1 tg1 sense2 + v fb2 i th2 track/ss2 ov3 tg2 sw2 23 22 21 20 9 10 11 12 t jmax = 150c, q ja = 34.7c/w exposed pad (pin 39) is pgnd, must be soldered to pcb pin configuration sen se1 + , sen se 2 + , sen se 1 C sen se 2 C voltages ..................................... C 0.3v to 28v sen se 3 + , sen se3 C voltages ..................... C 0.3v to 40v freq voltages ...................................... C 0.3v to intv cc extv cc ...................................................... C 0.3v to 14v i t h1 , i t h2 , i t h3 , v fb1 , v fb2 , v fb3 voltages .... C 0.3v to 6v pllin/mode, pgoo d1 , o v3 voltages ........ C 0.3v to 6v track/s s1 , track/s s2 , s s3 voltages ..... C 0.3v to 6v operating junction temperature range (note 2) lt c3859 a e, lt c3859 ai ..................... C 40 c to 125 c lt c3859 a h ........................................ C 40 c to 150 c lt c3859 a mp ..................................... C 55 c to 150 c storage temperature range .............. C 65 c to 150 c downloaded from: http:///
ltc3859a 3 3859afa electrical characteristics order information symbol parameter conditions min typ max units v bias bias input supply operating voltage range 4.5 38 v v fb1 ,2 buck regulated feedback voltage (note 4); i th1 ,2 voltage = 1.2v C40c to 85c, all grades ltc3859ae, ltc3859ai ltc3859ah, ltc3859amp l l 0.792 0.788 0.786 0.800 0.800 0.800 0.808 0.812 0.812 v v v v fb3 boost regulated feedback voltage (note 4); i th3 voltage = 1.2v C40c to 85c, all grades ltc3859ae, ltc3859ai ltc3859ah, ltc3859amp l l 1.188 1.182 1.179 1.200 1.200 1.200 1.212 1.218 1.218 v v v i fb1 ,2,3 feedback current (note 4) C10 50 na v reflnreg reference voltage line regulation (note 4); v in = 4v to 38v 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop; d i th voltage = 1.2v to 0.7v l 0.01 0.1 % measured in servo loop; d i th voltage = 1.2v to 2v l C0.01 C0.1 % g m1 ,2,3 transconductance amplifier g m (note 4); i th1 ,2,3 = 1.2v; sink/source 5a 2 mmho the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v bias = 12v, v run1,2,3 = 5v, extv cc = 0v unless otherwise noted. (note 2) lead free finish tape and reel part marking* package description temperature range ltc3859aefe#pbf ltc3859aefe#trpbf ltc3859afe 38-lead plastic tssop C40c to 125c ltc3859aife#pbf ltc3859aife#trpbf ltc3859afe 38-lead plastic tssop C40c to 125c ltc3859ahfe#pbf ltc3859ahfe#trpbf ltc3859afe 38-lead plastic tssop C40c to 150c ltc3859ampfe#pbf ltc3859ampfe#trpbf ltc3859afe 38-lead plastic tssop C55c to 150c ltc3859aeuhf#pbf ltc3859aeuhf#trpbf 3859a 38-lead (5mm 7mm) plastic qfn C40c to 125c ltc3859aiuhf#pbf ltc3859aiuhf#trpbf 3859a 38-lead (5mm 7mm) plastic qfn C40c to 125c ltc3859ahuhf#pbf ltc3859ahuhf#trpbf 3859a 38-lead (5mm 7mm) plastic qfn C40c to 150c ltc3859ampuhf#pbf ltc3859ampuhf#trpbf 3859a 38-lead (5mm 7mm) plastic qfn C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ . some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. http://www.linear.com/product/ltc3859a#orderinfo downloaded from: http:///
ltc3859a 4 3859afa electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v bias = 12v, v run1,2,3 = 5v, extv cc = 0v unless otherwise noted. (note 2) symbol parameter conditions min typ max units i q input dc supply current (note 5) pulse-skipping or forced continuous mode (one channel on) run1 = 5v and run2, 3 = 0v or run2 = 5v and run1,3 = 0v or run3 = 5v and run1,2 = 0v v fb1, 2 on = 0.83v (no load) v fb3 = 1.25v 1.5 ma pulse-skipping or forced continuous mode (all channels on) run1,2,3 = 5v, v fb1 ,2 = 0.83v (no load) v fb3 = 1.25v 3 ma sleep mode (one channel on, buck) run1 = 5v and run2,3 = 0v or run2 = 5v and run1,3 = 0v v fb,on = 0.83v (no load) 55 80 a sleep mode (one channel on, boost) run3 = 5v and run1,2 = 0v v fb3 = 1.25v 55 80 a sleep mode (buck and boost channel on) run1 = 5v and run2 = 0v or run2 = 5v and run1 = 0v run3 = 5v v fb1 ,2 = 0.83v (no load) v fb3 = 1.25v 65 100 a sleep mode (all three channels on) run1,2,3 = 5v, v fb1 ,2 = 0.83v (no load) v fb3 = 1.25v 80 120 a shutdown run1,2,3 = 0v 14 30 a uvlo undervoltage lockout intv cc ramping up l 4.15 4.5 v intv cc ramping down l 3.5 3.8 4.0 v v ovl1 ,2 buck feedback overvoltage protection measured at v fb1 ,2 relative to regulated v fb1 ,2 7 10 13 % i sense1 ,2 + sense + pin current bucks (channels 1 and 2) 1 a i sense3 + sense + pin current boost (channel 3) 170 a i sense1 ,2 C sense C pin current bucks (channels 1 and 2) v out1,2 < v intvcc C 0.5v v out1,2 > v intvcc + 0.5v 700 2 a a i sense3 C sense C pin current boost (channel 3) v sense3 +, v sense3 C = 12v 1 a df max,tg maximum duty factor for tg bucks (channels 1,2) in dropout, freq = 0v boost (channel 3) in overvoltage 98 99 100 % % df max,bg maximum duty factor for bg bucks (channels 1,2) in overvoltage boost (channel 3) 100 96 % % i track/ss1 ,2 soft-start charge current v track/ss1 ,2 = 0v 0.7 1.0 1.4 a i ss3 soft-start charge current v ss3 = 0v 0.7 1.0 1.4 a v run1 on v run2 ,3 on run1 pin threshold run2,3 pin threshold v run1 rising v run2 ,3 rising l l 1.19 1.23 1.25 1.28 1.31 1.33 v v v run1,2,3 hyst run pin hysteresis 80 mv v sense1,2,3(max) maximum current sense threshold v fb1 ,2 = 0.7v, v sense1 ,2 C = 3.3v v fb1,2,3 = 1.1v, v sense3 + = 12v l 43 50 57 mv v sense3(cm) sense3 pins common mode range (boost converter input supply voltage) 2.5 38 v downloaded from: http:///
ltc3859a 5 3859afa electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v bias = 12v, v run1,2,3 = 5v, extv cc = 0v unless otherwise noted. (note 2) symbol parameter conditions min typ max units gate driver tg1,2 pull-up on-resistance pull-down on-resistance 2.5 1.5 ? ? bg1,2 pull-up on-resistance pull-down on-resistance 2.4 1.1 ? ? tg3 pull-up on-resistance pull-down on-resistance 1.2 1.0 ? ? bg3 pull-up on-resistance pull-down on-resistance 1.2 1.0 ? ? tg1,2,3 t r tg1,2,3 t f tg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 16 ns ns bg1,2,3 t r bg1,2,3 t f bg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 28 13 ns ns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver bucks (channels 1, 2) boost (channel 3) 30 70 ns ns bg/tg t 1d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver bucks (channels 1, 2) boost (channel 3) 30 70 ns ns t on(min)1,2 buck minimum on-time (note 7) 95 ns t on(min)3 boost minimum on-time (note 7) 120 ns intv cc linear regulator v intvccvbias internal v cc voltage 6v < v bias < 38v, v extvcc = 0v, i intvcc = 0ma 5.0 5.4 5.6 v v ldovbias intv cc load regulation i cc = 0ma to 50ma, v extvcc = 0v 0.7 2 % v intvccext internal v cc voltage 6v < v extvcc < 13v, i intvcc = 0ma 5.0 5.4 5.6 v v ldoext intv cc load regulation i cc = 0ma to 50ma, v extvcc = 8.5v 0.7 2 % v extvcc extv cc switchover voltage extv cc ramping positive 4.5 4.7 v v ldohys extv cc hysteresis 200 mv oscillator and phase-locked loopf 25k programmable frequency r freq = 25k; pllin/mode = dc voltage 115 khz f 65k programmable frequency r freq = 65k; pllin/mode = dc voltage 375 440 505 khz f 105k programmable frequency r freq = 105k; pllin/mode = dc voltage 835 khz f low low fixed frequency v freq = 0v pllin/mode = dc voltage 320 350 380 khz f high high fixed frequency v freq = intv cc ; pllin/mode = dc voltage 485 535 585 khz f sync synchronizable frequency pllin/mode = external clock l 75 850 khz pgood1 outputv pgl1 pgood1 voltage low i pgood1 = 2ma 0.2 0.4 v i pgood1 pgood1 leakage current v pgood1 = 5v 1 a v pg1 pgood1 trip level v fb1 with respect to set regulated voltage v fb1 ramping negative C13 C10 C7 % hysteresis 2.5 % v fb1 ramping positive 7 10 13 % hysteresis 2.5 % downloaded from: http:///
ltc3859a 6 3859afa note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3859a is tested under pulsed load conditions such that t j t a . the ltc3859ae is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3859ai is guaranteed over the C40c to 125c operating junction temperature range, the ltc3859ah is guaranteed over the C40c to 150c operating junction temperature range and the ltc3859amp is tested and guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c . note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? q ja ), where q ja = 34c/w for the qfn package and q ja = 25c/w for the tssop package. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: the ltc3859a is tested in a feedback loop that servos v ith1,2,3 to a specified voltage and measures the resultant v fb . the specification at 85c is not tested in production and is assured by design, characterization and correlation to production testing at other temperatures (125c for the ltc3859ae/ltc3859ai, 150c for the ltc3859ah/ltc3859amp). for the ltc3859amp, the specification at C40c is not tested in production and is assured by design, characterization and correlation to production testing at C55c. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see the applications information section. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels.note 7: the minimum on-time condition is specified for an inductor peak-to-peak ripple current 40% of i max (see the minimum on-time considerations in the applications information section). electrical characteristics symbol parameter conditions min typ max units t pg1 delay for reporting a fault 20 s ov3 boost overvoltage indicator output v ov3l ov3 voltage low i ov3 = 2ma 0.2 0.4 v i ov3 ov3 leakage current v ov3 = 5v 1 a v ov ov3 trip level v fb with respect to set regulated voltage 6 10 13 % hysteresis 1.5 % boost3 charge pumpi bst3 boost3 charge pump available output current v boost3 = 16v; v sw3 = 12v; forced continuous mode 65 a the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v bias = 12v, v run1,2,3 = 5v, extv cc = 0v unless otherwise noted. (note 2) downloaded from: http:///
ltc3859a 7 3859afa typical performance characteristics load step (buck) burst mode operation load step (buck) forced continuous mode load step (buck) pulse-skipping mode inductor current at light load (buck) soft start-up buck regulated feedback voltage vs temperature efficiency and power loss vs output current (buck) efficiency vs output current (buck) efficiency vs input voltage (buck) output current (a) 0.0001 efficiency (%) power loss (mw) 100 9070 50 30 10 8060 40 20 0 10000100 1 1000 10 0.1 1 10 0.01 3859a g01 0.1 0.001 figure 12 circuitv in = 10v, v out = 5v fcm efficiencypulse-skipping efficiency burst loss burst efficiency fcm loss pulse-skipping loss output current (a) 0.0001 efficiency (%) 100 9070 50 30 10 8060 40 20 0 1 10 0.01 3859a g02 0.1 0.001 v in = 10v v in = 20v figure 12 circuitv out = 5v input voltage (v) 0 efficiency (%) 100 9997 95 93 9896 94 92 20 25 30 35 40 10 3859a g03 15 5 figure 12 circuitv out = 5v i load = 4a 50s/div v out 100mv/div ac-coupled i l 2a//div v in = 12v v out = 5v figure 12 circuit 3859a g04 50s/div v out 100mv/div ac-coupled i l 2a//div v in = 12v v out = 5v figure 12 circuit 3859a g05 50s/div v out 100mv/div ac-coupled i l 2a//div v in = 12v v out = 5v figure 12 circuit 3859a g06 2s/div forced continuous mode burst mode operation 1a/div pulse- skipping mode v in = 10v v out = 5v i load = 1ma figure 12 circuit 3859a g07 20ms/div v out2 2v/div v out1 2v/div 3859a g08 figure 12 circuit temperature (c) C75 regulated feedback voltage (mv) 808806 802 798 794 804800 796 792 0 25 50 75 150 125 100 C50 3859a g09 C25 downloaded from: http:///
ltc3859a 8 3859afa typical performance characteristics load step (boost) burst mode operation load step (boost) pulse-skipping mode load step (boost) forced continuous mode inductor current at light load (boost) soft start-up (boost) boost regulated feedback voltage vs temperature efficiency and power loss vs output current (boost) efficiency vs output current (boost) efficiency vs input voltage (boost) output current (a) 0.0001 efficiency (%) power loss (mw) 100 9070 50 30 10 8060 40 20 0 10000100 1 1000 10 0.1 1 10 0.01 3859a g10 0.1 0.001 figure 12 circuitv in = 5v, v out = 10v, v bias = v in fcm efficiencypulse-skipping efficiency burst loss burst efficiency fcm loss pulse-skipping loss output current (a) 0.0001 efficiency (%) 100 9070 50 30 10 8060 40 20 0 1 10 0.01 3859a g11 0.1 0.001 v in = 5v figure 12 circuitv bias = v in v out = 10v v in = 8v input voltage (v) 2 efficiency (%) 100 9997 95 91 92 93 9896 94 90 6 7 8 9 10 4 3 3859a g12 5 figure 12 circuitv bias = v in v out = 10v i load = 2a 200s/div v out 100mv/ divac- coupled i l 5a/div 3859a g13 v out = 10v v in = 5v figure 12 circuit 200s/div v out 100mv/div ac-coupled i l 5a/div 3859a g14 v out = 10v v in = 5v figure 12 circuit 200s/div v out 100mv/div ac-coupled i l 5a/div 3859a g15 v out = 10v v in = 5v figure 12 circuit 2s/div forced continuous mode burst mode operation 5a/div pulse- skipping mode 3859a g16 v out = 10v v in = 7v i load = 1ma figure 12 circuit 20ms/div v out3 2v/div gnd 3859a g17 v in = 5v figure 12 circuit temperature (c) C75 regulated feedback voltage (v) 1.2121.209 1.203 1.191 1.194 1.197 1.2061.200 1.188 0 25 50 75 150 120 100 C50 3859a g18 C25 downloaded from: http:///
ltc3859a 9 3859afa typical performance characteristics sense pins total input current vs v sense voltage buck sense C pin input bias current vs temperature boost sense pin total input current vs temperature maximum current sense threshold vs duty cycle maximum current sense threshold vs i th voltage track/ss pull-up current vs temperature intv cc line regulation intv cc and extv cc vs load current extv cc switchover and intv cc voltages vs temperature input voltage (v) 0 intv cc voltage (v) 5.55.4 5.2 5.35.1 5.0 15 20 25 30 35 40 5 3859a g19 10 load current (ma) 0 intv cc voltage (v) 5.65.2 5.44.6 4.8 5.04.4 4.2 4.0 60 80 100 20 3859a g20 40 extv cc = 0v extv cc = 5v extv cc = 8.5v v bias = 12v temperature (c) C75 extv cc and intv cc voltage (v) 6.05.8 5.4 5.2 4.4 4.2 4.6 4.8 5.65.0 4.0 0 25 50 75 150 125 100 C50 3859a g21 C25 intv cc extv cc rising extv cc falling v sense common mode voltage (v) 0 sense current (a) 800700 400 500300 100 200 600 0 15 20 25 30 35 40 5 3859a g22 10 sense1, 2 pins sense3 pin temperature (c) C75 sense current (a) 900700 800400 500300 100 200 600 0 0 25 50 75 100 125 150 C50 3859a g23 C25 v out < intv cc C 0.5v v out > intv cc + 0.5v temperature (c) C75 sense current (a) 200160 180100 120 8040 20 60 140 0 0 25 50 75 100 125 150 C50 3859a g24 C25 sense3 + pin sense3 C pin v in = 12v duty cycle (%) 0 maximum current sense voltage (mv) 8060 7030 4020 10 50 0 50 60 70 80 90 100 10 3859a g25 20 30 40 boost buck i th (v) 0 maximum current sense voltage (mv) 6040 50 C10 0 C20 3020 10 C30 1 1.2 1.4 0.2 3859a g26 0.4 0.6 0.8 burst mode operation pulse-skippingforced continuous temperature (c) C75 track/ss current (a) 1.201.15 1.05 1.00 0.85 0.90 1.100.95 0.80 0 25 50 75 125 100 150 C50 3859a g27 C25 downloaded from: http:///
ltc3859a 10 3859afa typical performance characteristics buck foldback current limit oscillator frequency vs temperature undervoltage lockout threshold vs temperature shutdown (run) threshold vs temperature charge pump charging current vs operating frequency charge pump charging current vs switch voltage shutdown current vs temperature shutdown current vs input voltage quiescent current vs temperature temperature (c) C75 shutdown current (a) 2220 16 14 10 1812 8 0 25 50 75 100 125 150 C50 3859a g28 C25 v bias = 12v v bias input voltage (v) 5 shutdown current (a) 2520 15 5 10 0 20 25 30 35 40 10 3859a g29 15 temperature (c) C75 quiescent current (a) 100 9080 50 60 7040 0 25 50 75 100 125 150 C50 3859a g30 C25 one channel on all channels on v bias = 12v feedback voltage (mv) 0 maximum current sense voltage (mv) 7060 50 20 10 30 40 6555 45 15 5 25 35 0 300 400 500 600 700 800 100 3859a g31 200 temperature (c) C75 frequency (khz) 600550 500 350 400 450300 0 25 50 75 100 125 150 C50 3859a g32 C25 freq = intv cc freq = gnd temperature (c) C75 intv cc voltage (v) 4.44.3 4.2 3.6 3.8 4.03.4 3.5 3.7 3.9 4.1 0 25 50 75 100 125 150 C50 3859a g33 C25 rising falling temperature (c) C75 run pin voltage (v) 1.401.35 1.30 1.20 1.00 1.151.10 1.05 1.25 0 25 50 75 100 125 150 C50 3859a g34 C25 run1 rising run1 falling run2,3 falling run2,3 rising operating frequency (khz) 100 charge pump charging current (a) 100 80 9060 7020 30 0 10 40 50 400 500 600 700 800 200 3859a g35 300 C55c 25c 150c v boost3 = 16v v sw3 = 12v switch voltage (v) 5 charge pump charging current (a) 100 80 9060 7020 30 0 10 40 50 20 25 30 35 40 10 3859a g36 freq = 0v freq = intv cc 15 v boost3 C v sw3 = 4v downloaded from: http:///
ltc3859a 11 3859afa pin functions freq (pin 1/pin 5) : the frequency control pin for the internal vco. connecting the pin to gnd forces the vco to a fixed low frequency of 350khz . connecting the pin to intv cc forces the vco to a fixed high frequency of 535khz . other frequencies between 50khz and 900khz can be programmed using a resistor between freq and gnd. the resistor and an internal 20a source current create a voltage used by the internal oscillator to set the frequency. pllin/mode (pin 2/pin 6) : external synchronization input to phase detector and forced continuous mode input. when an external clock is applied to this pin, the phase-locked loop will force the rising t g1 signal to be synchronized with the rising edge of the external clock, and the regulators operate in forced continuous mode. when not synchronizing to an external clock, this input, which acts on all three controllers, determines how the ltc3859 aa operates at light loads. pulling this pin to ground selects burst mode operation. an internal 100k resistor to ground also invokes burst mode operation when the pin is floated. tying this pin to intv cc forces continuous inductor current operation. tying this pin to a voltage greater than 1.2v and less than intv cc C 1.3v selects pulse-skipping operation. this can be done by connecting a 100k resistor from this pin to intv cc . sgnd (pin 8/pin 12) : small signal ground common to all three controllers, must be routed separately from high current grounds to the common ( C ) terminals of the c in capacitors.run1 , ru n2 , ru n3 (pins 9, 10, 11/pins 13, 14, 15) : digital run control inputs for each controller. forcing run1 below 1.17v and ru n2/run3 below 1.20v shuts down that controller. forcing all of these pins below 0.7v shuts down the entire ltc3859 a, reducing quiescent current to approximately 14a.o v3 (pin 17/pin 21) : overvoltage open-drain logic output for the boost regulator. o v3 is pulled to ground when the voltage on the v fb3 pin is under 110% of its set point, and becomes high impedance when v fb3 goes over 110% of its set point. intv cc (pin 22/pin 26) : output of the internal linear low dropout regulator. the driver and control circuits are pow - ered from this voltage source. must be decoupled to pgnd with a minimum of 4.7f ceramic or tantalum capacitor . extv cc (pin 23/pin 27) : external power input to an internal ldo connected to intv cc . this ldo supplies intv cc power, bypassing the internal ldo powered from v bias whenever extv cc is higher than 4.7v . see extv cc connection in the applications information section. do not float or exceed 14v on this pin. v bias (pin 24/pin 28) : main bias input supply pin. a bypass capacitor should be tied between this pin and the sgnd pin. bg1, bg2, bg3 (pins 29, 21, 25/pins 33, 25, 29): high current gate drives for bottom (synchronous) n-channel mosfets. voltage swing at these pins is from ground to intv cc . boost1, boost2, boost3 (pins 30, 20, 26/pins 34, 24, 30) : bootstrapped supplies to the top side floating drivers. capacitors are connected between the boost and sw pins and schottky diodes are tied between the boost and intv cc pins. voltage swing at the boost pins is from intv cc to (v in + intv cc ). sw1, sw2, sw3 (pins 31, 19, 28/pins 35, 23, 32) : switch node connections to inductors.tg1 , t g2 , t g3 (pins 32, 18, 27/pins 36, 22, 31) : high current gate drives for top n-channel mosfets. these are the outputs of floating drivers with a voltage swing equal to intv cc superimposed on the switch node voltage sw. pgood1 (pin 33/pin 37) : open-drain logic output. pgood1 is pulled to ground when the voltage on the v fb1 pin is not within 10% of its set point. (qfn/tssop) downloaded from: http:///
ltc3859a 12 3859afa pin functions track/ss1 , track/s s2 , s s3 (pins 34, 16, 3/pins 38, 20, 7) : external tracking and soft-start input. for the buck channels, the ltc3859 a regulates the v fb1,2 voltage to the smaller of 0.8v , or the voltage on the track/s s1 ,2 pin. for the boost channel, the ltc3859 a regulates the v fb3 voltage to the smaller of 1.2v , or the voltage on the s s3 pin. an internal 1a pull-up current source is connected to this pin. a capacitor to ground at this pin sets the ramp time to final regulated output voltage. alternatively, a re - sistor divider on another voltage supply connected to the track/ss pins of the buck channels allow the ltc3859a buck outputs to track the other supply during start-up.i th1 , i th2 , i th3 (pins 35, 15, 7/pins 1, 19, 11) : error amplifier outputs and switching regulator compensation points. each associated channel s current comparator trip point increases with this control voltage. v fb1 , v fb2 , v fb3 (pins 36, 14, 6/pins 2, 18, 10) : receives the remotely sensed feedback voltage for each controller from an external resistive divider across the output. sense1 + , sen se2 + , sen se3 + (pins 37, 13, 4/pins 3, 17, 8) : the (+) input to the differential current comparators. the i th pin voltage and controlled offsets between the sense C and sense + pins in conjunction with r sense set the current trip threshold. for the boost channel, the sense3 + pin supplies current to the current comparator. sense1 C , sen se2 C , sen se3 C (pins 38, 12, 5/pins 4, 16, 9) : the ( C ) input to the differential current compara - tors. when sen se1,2 C for the buck channels is greater than intv cc , then sen se1,2 C pin supplies current to the current comparator. pgnd (exposed pad pin 39) : driver power ground. con - nects to the sources of bottom n-channel mosfets and the (C ) terminal(s) of c in . the exposed pad must be soldered to the pcb for rated electrical and thermal performance. (qfn/tssop) downloaded from: http:///
ltc3859a 13 3859afa functional diagram 3859a bd switching logic intv cc v in1,2 d b c b boost tg sw bg pgnd sense + sense C c in d c out intv cc l r sense topbot dropout det s q r q bot topon shdn + C sleep +C +C + C + C icmp ir 2.8v 0.65v slope comp v fb i th 3mv 0.80vtrack/ss 0.88v +C C+ + track/ss ov c c2 rc c c run c ss foldback shdn r st 2(v fb ) shdn 6a ch10.5a ch2 11v pfd vco c lp clk2clk1 sync det 20a 100k r a r b ldo en ldo en + C 4.7v 5.4v 5.4v intv cc sgnd extv cc v bias freqpllin/mode pgood1 +C +C 0.88v0.72v v fb1 ea buck channels 1 and 2 1a v out1,2 6.8v downloaded from: http:///
ltc3859a 14 3859afa functional diagram 3859a bd switching logic intv cc v out3 d b c b boost3 tg3 sw3 bg3 pgnd sense3 + sense3 C c out c in intv cc l r sense topbot s q r q boton shdn +C sleep +C +C + C + C icmp ir 2.8v0.7v slope comp v fb3 v out3 i th3 2mv 1.2vss3 1.32v +C C+ + ss3 ov c c2 r c c c run3 c ss shdn snslo 0.5a 11v r a r b ea +C 2v snslo clk1 pllin/mode +C v fb3 1.32v ov3 0.425v boost channel 3 1a v in3 downloaded from: http:///
ltc3859a 15 3859afa operation main control loop the ltc3859a uses a constant frequency, current mode step-down architecture. the two buck controllers, chan - nels 1 and 2, operate 180 degrees out of phase with each other. the boost controller, channel 3, operates in phase with channel 1. during normal operation, the external top mosfet for the buck channels (the external bottom mosfet for the boost channel) is turned on when the clock for that channel sets the rs latch, and is turned off when the main current comparator, icmp, resets the rs latch. the peak inductor current at which icmp trips and resets the latch is controlled by the voltage on the i th pin, which is the output of the error amplifier ea. the error amplifier compares the output voltage feedback signal at the v fb pin, (which is generated with an external resistor divider connected across the output voltage, v out , to ground) to the internal 0.800v reference voltage for the bucks ( 1.2v reference voltage for the boost). when the load current increases, it causes a slight decrease in v fb relative to the reference, which causes the ea to increase the i th voltage until the average inductor current matches the new load current.after the top mosfet for the bucks (the bottom mosfet for the boost) is turned off each cycle, the bottom mosfet is turned on (the top mosfet for the boost) until either the inductor current starts to reverse, as indicated by the current comparator ir, or the beginning of the next clock cycle. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open or tied to a voltage less than 4.7v , the v bias ldo (low dropout linear regulator) supplies 5.4v from v bias to intv cc . if extv cc is taken above 4.7v , the v bias ldo is turned off and an extv cc ldo is turned on. once enabled, the extv cc ldo supplies 5.4v from extv cc to intv cc . using the extv cc pin allows the intv cc power to be derived from a high efficiency external source such as one of the ltc3859 a switching regulator outputs. each top mosfet driver is biased from the floating boot - strap capacitor c b , which normally recharges during each cycle through an external diode when the switch voltage goes low. for buck channels 1 and 2, if the buck s input voltage decreases to a voltage close to its output, the loop may enter dropout and attempt to turn on the top mosfet con - tinuously. the dropout detector detects this and forces the top mosfet off for about one twelfth of the clock period every tenth cycle to allow c b to recharge. shutdown and start-up (run1, run2, run3 and track/ss1, track/ss2, ss3 pins) the three channels of the ltc3859 a can be independently shut down using the ru n1 , ru n2 and ru n3 pins. pulling run1 below 1.17v and ru n2/run3 below 1.20v shuts down the main control loop for that channel. pulling all three pins below 0.7v disables all controllers and most internal circuits, including the intv cc ldos. in this state, the ltc3859a draws only 14a of quiescent current. releasing a run pin allows a small internal current to pull up the pin to enable that controller. the ru n1 pin has a 6a pull-up current while the ru n2 and ru n3 pins have a smaller 0.5a . the 6a current on ru n1 is designed to be large enough so that the ru n1 pin can be safely floated (to always enable the controller) without worry of condensation or other small board leakage pulling the pin down. this is ideal for always-on applications where one or more controllers are enabled continuously and never shut down. each run pin may also be externally pulled up or driven directly by logic. when driving a run pin with a low imped - ance source, do not exceed the absolute maximum rating of 8v . each run pin has an internal 11v voltage clamp that allows the run pin to be connected through a resistor to a higher voltage (for example, v bias ), so long as the maximum current in the run pin does not exceed 100a. the start-up of each channel s output voltage v out is con - trolled by the voltage on the track/ss pin (track/s s1 for channel 1, track/s s2 for channel 2, s s3 for channel 3). when the voltage on the track/ss pin is less than the 0.8v internal reference for the bucks and the 1.2v internal (refer to functional diagram) downloaded from: http:///
ltc3859a 16 3859afa operation reference for the boost, the ltc3859 a regulates the v fb voltage to the track/ss pin voltage instead of the cor - responding reference voltage. this allows the track/ss pin to be used to program a soft-start by connecting an external capacitor from the track/ss pin to sgnd. an internal 1a pull-up current charges this capacitor creating a voltage ramp on the track/ss pin. as the track/ss voltage rises linearly from 0v to 0.8v/1.2v (and beyond up to intv cc ), the output voltage v out rises smoothly from zero to its final value. alternatively the track/ss pins for buck channels 1 and 2 can be used to cause the start-up of v out to track that of another supply. typically, this requires connecting to the track/ss pin an external resistor divider from the other supply to ground (see the applications information section). light load current operation (burst mode operation, pulse-skipping, or continuous conduction) (pllin/mode pin) the ltc3859 a can be enabled to enter high efficiency burst mode operation, constant frequency pulse-skipping mode or forced continuous conduction mode at low load currents. to select burst mode operation, tie the pllin/ mode pin to ground. to select forced continuous opera - tion, tie the pllin/mode pin to intv cc . to select pulse- skipping mode, tie the pllin/mode pin to a dc voltage greater than 1.2v and less than intv cc C 1.3v. when a controller is enabled for burst mode operation, the minimum peak current in the inductor is set to approxi - mately 25% of the maximum sense voltage (30% for the boost) even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier ea will decrease the voltage on the i th pin. when the i th voltage drops below 0.425v , the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. the i th pin is then disconnected from the output of the ea and parked at 0.450v. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the ltc3859 a draws. if one channel is in sleep mode and the other two are shut down, the ltc3859 a draws only 55a of quiescent current. if two channels are in sleep mode and the other shut down, it draws only 65a of quiescent current. if all three controllers are enabled in sleep mode, the ltc3859 a draws only 80a of quiescent. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the ea s output begins to rise. when the output voltage drops enough, the i th pin is reconnected to the output of the ea, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (ir) turns off the bottom external mosfet (the top external mosfet for the boost) just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller operates in discontinuous operation. in forced continuous operation or clocked by an external clock source to use the phase-locked loop (see the fre - quency selection and phase-locked loop section), the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor cur - rent is determined by the voltage on the i th pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous operation has the advantage of lower output voltage ripple and less interference to audio circuitry. in forced continuous mode, the output ripple is independent of load current. when the pllin/mode pin is connected for pulse-skipping mode, the ltc3859 a operates in pwm pulse-skipping mode at light loads. in this mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. at very light loads, the current comparator icmp may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. downloaded from: http:///
ltc3859a 17 3859afa operation frequency selection and phase-locked loop (freq and pllin/mode pins) the selection of switching frequency is a trade-off between efficiency and component size. low frequency opera - tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the ltc3859a s controllers can be selected using the freq pin.if the pllin/mode pin is not being driven by an external clock source, the freq pin can be tied to sgnd, tied to intv cc , or programmed through an external resistor. ty - ing freq to sgnd selects 350khz while tying freq to intv cc selects 535khz . placing a resistor between freq and sgnd allows the frequency to be programmed between 50khz and 900khz. a phase-locked loop (pll) is available on the ltc3859a to synchronize the internal oscillator to an external clock source that is connected to the pllin/mode pin. the ltc3859a s phase detector adjusts the voltage (through an internal lowpass filter) of the vco input to align the turn-on of controller 1 s external top mosfet to the ris - ing edge of the synchronizing signal. thus, the turn-on of controller 2 s external top mosfet is 180 degrees out of phase to the rising edge of the external clock source. the vco input voltage is pre-biased to the operating frequency set by the freq pin before the external clock is applied. if prebiased near the external clock frequency, the pll loop only needs to make slight changes to the vco input in order to synchronize the rising edge of the external clock s to the rising edge of t g1 . the ability to pre-bias the loop filter allows the pll to lock in rapidly without deviating far from the desired frequency. the typical capture range of the ltc3859a s phase-locked loop is from approximately 55khz to 1mhz , with a guar - antee over all manufacturing variations to be between 75khz and 850khz . in other words, the ltc3859a s pll is guaranteed to lock to an external clock source whose frequency is between 75khz and 850khz. the typical input clock thresholds on the pllin/mode pin are 1.6v (rising) and 1.2v (falling). boost controller operation when v in > v out when the input voltage to the boost channel rises above its regulated v out voltage, the controller can behave dif - ferently depending on the mode, inductor current and v in voltage. in forced continuous mode, the loop works to keep the top mosfet on continuously once v in rises above v out . an internal charge pump delivers current to the boost capacitor from the boost3 pin to maintain a sufficiently high tg voltage. (the amount of current the charge pump can deliver is characterized by two curves in the typical performance characteristics section.) in pulse-skipping mode, if v in is between 100% and 110% of the regulated v out voltage, t g3 turns on if the inductor current rises above approximately 3% of the programmed i lim current. if the part is programmed in burst mode operation under this same v in window, then tg3 turns on at the same threshold current as long as the chip is awake (one of the buck channels is awake and switching). if both buck channels are asleep or shut down in this v in window, then t g3 will remain off regardless of the inductor current.if v in rises above 110% of the regulated v out voltage in any mode, the controller turns on t g3 regardless of the inductor current. in burst mode operation, however, the internal charge pump turns off if the entire chip is asleep (the two buck channels are asleep or shut down). with the charge pump off, there would be nothing to prevent the boost capacitor from discharging, resulting in an insufficient tg voltage needed to keep the top mosfet completely on. the charge pump turns back on when the chip wakes up, and it remains on as long as one of the buck channels is actively switching. boost controller at low sense pin common voltage the current comparator of the boost controller is powered directly from the sen se3 + pin and can operate to voltages as low as 2.5v . since this is lower than the v bias uvlo of the chip, v bias can be connected to the output of the boost controller, as illustrated in the typical application circuit in figure 12. this allows the boost controller to handle input voltage transients down to 2.5v while maintaining output voltage regulation. if the sen se3 + rises back above 2.5v , the s s3 pin will be released initiating a new soft-start sequence. downloaded from: http:///
ltc3859a 18 3859afa buck controller output overvoltage protection the two buck channels have an overvoltage comparator that guards against transient overshoots as well as other more serious conditions that may overvoltage their outputs. when the v fb1 ,2 pin rises by more than 10% above its regulation point of 0.800v , the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. channel 1 power good (pgood1) channel 1 has a pgoo d1 pin that is connected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgoo d1 pin low when the v fb1 pin voltage is not within 10% of the 0.8v reference voltage for the buck channel. the pgoo d1 pin is also pulled low when the ru n1 pin is low (shut down). when the v fb1 pin voltage is within the 10% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source no greater than 6v. boost overvoltage indicator (ov3) the o v3 pin is an overvoltage indicator that signals whether the output voltage of the channel 3 boost controller goes over its programmed regulated voltage. the pin is con - nected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the o v3 pin low when the v fb3 pin voltage is less than 110% of the 1.2v reference voltage for the boost channel. the o v3 pin is also pulled low when the ru n3 pin is low (shut down). when the v fb3 pin voltage goes higher than 110% of the 1.2v reference, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source no greater than 6v. buck foldback current when the buck output voltage falls to less than 70% of its nominal level, foldback current limiting is activated, progressively lowering the peak current limit in proportion to the severity of the overcurrent or short-circuit condition. foldback current limiting is disabled during the soft-start interval (as long as the v fb voltage is keeping up with the track/s s1 ,2 voltage). there is no foldback current limiting for the boost channel. theory and benefits of 2-phase operation why the need for 2- phase operation ? up until the 2-phase family, constant-frequency dual switching regulators operated both channels in phase (i.e., single-phase operation). this means that both switches turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor and battery. these large amplitude current pulses increased the total rms current flowing from the input capacitor, requiring the use of more expensive input capacitors and increasing both emi and losses in the input capacitor and battery. with 2- phase operation, the two buck controllers of the ltc3859 a are operated 180 degrees out of phase. this effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. the result is a significant reduction in total rms input current, which in turn allows less expensive input capacitors to be used, reduces shielding requirements for emi and improves real world operating efficiency. operation downloaded from: http:///
ltc3859a 19 3859afa operation figure 1 compares the input waveforms for a representative single-phase dual switching regulator to the 2- phase dual buck controllers of the ltc3859 a. an actual measure - ment of the rms input current under these conditions shows that 2- phase operation dropped the input current from 2.53a rms to 1.55a rms . while this is an impressive reduction in itself, remember that the power losses are proportional to i rms2 , meaning that the actual power wasted is reduced by a factor of 2.66. the reduced input ripple voltage also means less power is lost in the input power path, which could include batteries, switches, trace/con - nector resistances and protection circuitry. improvements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. of course, the improvement afforded by 2- phase opera - tion is a function of the dual switching regulator s relative duty cycles which, in turn, are dependent upon the input voltage v in (duty cycle = v out /v in ). figure 2 shows how the rms input current varies for single-phase and 2-phase operation for 3.3v and 5v regulators over a wide input voltage range. figure 1. input waveforms comparing single-phase (a) and 2-phase (b) operation for dual switching regulators converting 12v to 5v and 3.3v at 3a each. the reduced input ripple with the 2-phase regulator allows less expensive input capacitors, reduces shielding requirements for emi and improves efficiency figure 2. rms input current comparison (a) (b) it can readily be seen that the advantages of 2- phase op - eration are not just limited to a narrow operating range, for most applications is that 2- phase operation will reduce the input capacitor requirement to that for just one chan - nel operating at maximum current and 50% duty cycle. the schematic on the first page is a basic ltc3859 a ap - plication circuit. external component selection is driven by the load requirement, and begins with the selection of r sense and the inductor value. next, the power mosfets are selected. finally, c in and c out are selected. input voltage (v) 0 input rms current (a) 3.02.5 2.0 1.5 1.0 0.5 0 10 20 30 40 3859a f02 single phasedual controller 2-phase dual controller v o1 = 5v/3a v o2 = 3.3v/3a i in(meas) = 2.53a rms i in(meas) = 1.55a rms 3859a f01b 3859a f01a 5v switch 20v/div 3.3v switch 20v/div input current 5a/div input voltage 500mv/div downloaded from: http:///
ltc3859a 20 3859afa figure 3. sense lines placement with inductor or sense resistor applications information the typical application on the first page is a basic ltc3859 a application circuit. ltc3859 a can be configured to use either dcr (inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption, and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load requirement, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfets and schottky diodes are selected. finally, input and output capacitors are selected. sense + and sense C pins the sense + and sense C pins are the inputs to the cur - rent comparators. buck controllers (sense1 + /sense1 C ,sense2 + /sense2 C ): the common mode voltage range on these pins is 0v to 28v (absolute maximum), enabling the ltc3859 a to regulate buck output voltages up to a nominal 24v (al - lowing margin for tolerances and transients). the sense + pin is high impedance over the full common mode range, drawing at most 1a . this high impedance allows the current comparators to be used in inductor dcr sensing. the impedance of the sense C pin changes depending on the common mode voltage. when sense C is less than intv cc C0.5v , a small current of less than 1a flows out of the pin. when sense C is above intv cc +0.5v , a higher current ( 700a ) flows into the pin. between intv cc C 0.5v and intv cc + 0.5v , the current transitions from the smaller current to the higher current. boost controller (sen se3 + /sense3 C ): the common mode input range for these pins is 2.5v to 38v , allowing the boost converter to operate from inputs over this full range. the sen se3 + pin also provides power to the cur - rent comparator and draws about 170a during normal operation (when not shut down or asleep in burst mode operation). there is a small bias current of less than 1a that flows out of the sen se3 C pin. this high impedance on the sen se3 C pin allows the current comparator to be used in inductor dcr sensing.filter components mutual to the sense lines should be placed close to the ltc3859 a, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 3). sensing cur - rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if dcr sensing is used (figure 4b ), sense resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. low value resistor current sensing a typical sensing circuit using a discrete resistor is shown in figure 4a . r sense is chosen based on the required output current.the current comparators have a maximum threshold v sense(max) of 50mv . the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current, i max , equal to the peak value less half the peak-to-peak ripple current, d i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + d i l 2 when using the buck controllers in very low dropout conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for buck regulators operating at greater than 50% duty factor. a curve is provided in the typical performance characteristics section to estimate this reduction in peak output current level depending upon the operating duty factor. 3859a f03 to sense filter next to the controller inductor or r sense current flow downloaded from: http:///
ltc3859a 21 3859afa applications information inductor dcr sensing for applications requiring the highest possible efficiency at high load currents, the ltc3859 a is capable of sensing the voltage drop across the inductor dcr, as shown in figure 4b . the dcr of the inductor represents the small amount of dc winding resistance of the copper, which can be less than 1m for today s low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of efficiency compared to dcr sensing. if the external r1||r2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature ; consult the manufacturers data sheets for detailed information.using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is : r (equiv) = v sense(max) i max + d i l 2 to ensure that the application will deliver full load cur - rent over the full operating temperature range, determine r sense(equiv) , keeping in mind that the maximum current sense threshold (v sense(max) ) for the ltc3859 a is fixed at 50mv. next, determine the dcr of the inductor. where provided, use the manufacturer s maximum value, usually given at 20c . increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/ c. a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor value, use the divider ratio: r d = r sense(equiv) dcr max at t l(max) c1 is usually selected to be in the range of 0.1f to 0.47f. this forces r1||r2 to around 2k , reducing error that might have been caused by the sense + pins 1a current. the equivalent resistance r1||r2 is scaled to the room temperature inductance and maximum dcr: ? r1 ? r2 = l (dcr at 20 c) ? c 1 the sense resistor values are: ? r1 = r1 ? r2 r d ; r2 = r1 ? r d 1 ? r d 4b. using the inductor dcr to sense current 4a. using a resistor to sense current figure 4. current sensing methods 3859a f04a ltc3859a intv cc boost tg sw bg sense1,2 + (sense3 C ) sense1, 2 C (sense3 + ) sgnd v in1,2 (v out3 ) v out1,2 (v in3 ) r sense capplaced near sense pins 3859a f04b ltc3859a intv cc boost tg sw bg sense1, 2 + (sense3 C ) sense1, 2 C (sense3 + ) sgnd v in1,2 (v out3 ) v out1,2 (v in3 ) c1* r2 *place c1 near sense pins r sense(eq) = dcr(r2/(r1+r2)) l dcr inductor r1 (r1||r2) ? c1 = l/dcr downloaded from: http:///
ltc3859a 22 3859afa applications information t he maximum power loss in r1 is related to duty cycle. for the buck controllers, the maximum power loss will occur in continuous mode at the maximum input voltage : p loss r1 = (v in(max) ? v out ) ? v out r1 for the boost controller, the maximum power loss in r1 will occur in continuous mode at v in = 1/2 ? v out : p loss r1 = (v out(max) ? v in ) ? v in r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1 . however, dcr sensing eliminates a sense resistor, reduces conduc - tion losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. inductor value calculation the operating frequency and inductor selection are inter - related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components ? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current d i l decreases with higher inductance or frequency. for the buck controllers, d i l increases with higher v in : d i l = 1 (f)(l) v out 1 ? v out v in ?? ? ?? ? for the boost controller, the inductor ripple current d i l increases with higher v out : d i l = 1 (f)(l) v in 1 ? v in v out ?? ? ?? ? accepting larger values of d i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is d i l = 0.3(i max ). the maximum d i l occurs at the maximum input voltage for the bucks and v in = 1/2 ? v out for the boost. the inductor value also has secondary effects. the tran - sition to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit (30% for the boost) determined by r sense . lower inductor values (higher d i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc - tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! downloaded from: http:///
ltc3859a 23 3859afa applications information power mosfet and schottky diode (optional) selection two external power mosfet s must be selected for each controller in the ltc3859 a: one n-channel mosfet for the top switch (main switch for the buck, synchronous for the boost), and one n-channel mosfet for the bottom switch (main switch for the boost, synchronous for the buck). the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5.4v during start-up (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. pay close attention to the bv dss specification for the mosfets as well; many of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance r ds(on) , miller capacitance c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: buck main switch duty cycle = v out v in buck sync switch duty cycle = v in ? v out v in boost main switch duty cycle = v out ? v in v out boost sync switch duty cycle = v in v out the mosfet power dissipations at maximum output current are given by: p main _ buck = v out v in i out(max) ( ) 2 1 + ( ) r ds(on) + (v in ) 2 i out(max) 2 ?? ? ?? ? (r dr )(c miller ) ? 1 v intvcc ? v thmin + 1 v thmin ?? ? ?? ? (f) p sync _ buck = v in ? v out v in i out(max) ( ) 2 1 + ( ) r ds(on) p main _ boost = v out ? v in ( ) v out v in 2 i out(max) ( ) 2 ? 1 + ( ) r ds(on) + v out 3 v in ?? ?? ?? ?? i out(max) 2 ?? ? ?? ? ? r dr ( ) c miller ( ) ? 1 v intvcc ? v thmin + 1 v thmin ?? ? ?? ? (f) p sync _ boost = v in v out i out(max) ( ) 2 1 + ( ) r ds(on) where z is the temperature dependency of r ds(on) and rdr (approximately 2 ) is the effective driver resistance at the mosfet s miller threshold voltage. v thmin is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the main n-channel equations for the buck and boost controllers include an additional term for transition losses, which are highest at high input voltages for the bucks and low input voltages for the boost. for v in < 20v (high v in for the boost) the high current efficiency generally improves with larger mosfets, while for v in > 20v (low v in for the boost) the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher downloaded from: http:///
ltc3859a 24 3859afa applications information efficiency. the synchronous mosfet losses for the buck controllers are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the synchronous mosfet losses for the boost controller are greatest when the input voltage approaches the output volt - age or during an overvoltage event when the synchronous switch is on 100% of the period. the term (1+ z ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but z = 0.005/ c can be used as an approximation for low voltage mosfets. the optional schottky diodes d4, d5 , and d6 shown in figure 13 conduct during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the synchronous mosfet from turning on, storing charge during the dead-time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. boost c in , c out selection the input ripple current in a boost converter is relatively low (compared with the output ripple current), because this current is continuous. the boost input capacitor c in voltage rating should comfortably exceed the maximum input voltage. although ceramic capacitors can be relatively tolerant of overvoltage conditions, aluminum electrolytic capacitors are not. be sure to characterize the input voltage for any possible overvoltage transients that could apply excess stress to the input capacitors. the value of c in is a function of the source impedance, and in general, the higher the source impedance, the higher the required input capacitance. the required amount of input capacitance is also greatly affected by the duty cycle. high output current applications that also experience high duty cycles can place great demands on the input supply, both in terms of dc current and ripple current. in a boost converter, the output has a discontinuous current, so c out must be capable of reducing the output voltage ripple. the effects of esr (equivalent series resistance) and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. the steady ripple due to charging and discharging the bulk capacitance is given by: ripple = i out(max) ? v out ? v in(min) ( ) c out ? v out ? f v where c out is the output filter capacitor. the steady ripple due to the voltage drop across the esr is given by: d v esr = i l(max) ? esr multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient. capacitors are now available with low esr and high ripple current ratings such as os-con and poscap. buck c in , c out selection the selection of c in for the two buck controllers is simplified by the 2- phase architecture and its impact on the worst- case rms current drawn through the input network (bat - tery/fuse/capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula shown in equa- tion (1) to determine the maximum rms capacitor current requirement. increasing the output current drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the out-of-phase technique typically reduces the input capacitor s rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. downloaded from: http:///
ltc3859a 25 3859afa applications information in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in ? v out ( ) ?? ?? 1/ 2 (1) this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3859 a, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question.the benefit of the ltc3859a 2- phase operation can be calculated by using equation (1) for the higher power con - troller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor s esr. this is why the input capacitor s requirement calculated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. the overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. the drains of the top mosfets should be placed within 1cm of each other and share a common c in (s). separat - ing the drains and c in may produce undesirable voltage and current resonances at v in . a small ( 0.1f to 1f ) bypass capacitor between the chip v in pin and ground, placed close to the ltc3859 a, is also suggested. a small ( 1 to 10 ) resistor placed between c in ( c1 ) and the v in pin provides further isolation between the two channels.the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple ( d v out ) is approximated by: d v out d i l esr + 1 8fc out ?? ? ?? ? where f is the operating frequency, c out is the output capacitance and d i l is the ripple current in the inductor. the output ripple is highest at maximum input voltage since d i l increases with input voltage. setting output voltage the ltc3859 a output voltages are each set by an external feedback resistor divider carefully placed across t he output, as shown in figure 5. the regulated output voltages are determined by: v out, buck = 0.8v 1 + r b r a ?? ? ?? ? v out, boost = 1.2v 1 + r b r a ?? ? ?? ? to improve the frequency response, a feedforward ca - pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. figure 5. setting output voltage 3859a f05 1/3 ltc3859a v fb r b c ff r a v out downloaded from: http:///
ltc3859a 26 3859afa applications information tracking and soft-start (track/ss1, track/ss2, ss3 pins) the start-up of each v out is controlled by the voltage on the respective track/ss pin (track/s s1 for channel 1, track/ss2 for channel 2, s s3 for channel 3). when the voltage on the track/ss pin is less than the internal 0.8v reference ( 1.2v reference for the boost channel), the ltc3859 a regulates the v fb pin voltage to the voltage on the track/ss pin instead of the internal reference. likewise, the track/ss pin for the buck channels can be used to program an external soft-start function or to allow v out to track another supply during start-up. soft-start is enabled by simply connecting a capacitor from the track/ss pin to ground, as shown in figure 6. an internal 1a current source charges the capacitor, providing a linear ramping voltage at the track/ss pin. the ltc3859 a will regulate the v fb pin (and hence v out ) according to the voltage on the track/ss pin, allowing v out to rise smoothly from 0v to its final regulated value. the total soft-start time will be approximately: t ss _ buck = c ss ? 0.8v 1a t ss _ boost = c ss ? 1.2v 1a alternatively, the track/s s1 and track/s s2 pins for the two buck controllers can be used to track two (or more) sup - plies during start-up, as shown qualitatively in figures 7a and 7b . to do this, a resistor divider should be connected from the master supply (v x ) to the track/ss pin of the slave supply (v out ), as shown in figure 8. during start-up v out will track v x according to the ratio set by the resis - tor divider: v x v out = r a r tracka ? r tracka + r trackb r a + r b for coincident tracking (v out = v x during start-up), r a = r tracka r b = r trackb 7a. coincident tracking 7b. ratiometric tracking figure 7. two different modes of output voltage tracking figure 8. using the track/ss pin for tracking 3859a f07a v x(master) v out(slave) output (v out ) time 3859a f07b v x(master) v out(slave) output (v out ) time 3859a f08 ltc3859a v fb1,2 track/ss1,2 r b r a v out r trackb r tracka v x figure 6. using the track/ss pin to program soft-start 3859a f06 1/3 ltc3859a track/sssgnd c ss downloaded from: http:///
ltc3859a 27 3859afa applications information intv cc regulators the ltc3859 a features two separate internal p-channel low dropout linear regulators (ldo) that supply power at the intv cc pin from either the v bias supply pin or the extv cc pin depending on the connection of the extv cc pin. intv cc powers the gate drivers and much of the ltc3859a s internal circuitry. the v bias ldo and the extv cc ldo regulate intv cc to 5.4v . each of these must be bypassed to ground with a minimum of 4.7f ceramic capacitor. no matter what type of bulk capacitor is used, an additional 1f ceramic capacitor placed directly adjacent to the intv cc and pgnd ic pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi - mum junction temperature rating for the ltc3859 a to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the v bias ldo or the extv cc ldo. when the voltage on the extv cc pin is less than 4.7v , the v bias ldo is enabled. power dissipation for the ic in this case is highest and is equal to v bias ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. the junction temperature can be estimated by using the equations given in note 2 of the electrical characteristics. for example, the ltc3859a intv cc current is limited to less than 40ma from a 40v supply when not using the extv cc supply at a 70c ambi - ent temperature in the qfn package: t j = 70c + (40ma)(40v)(34c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (pllin/mode = intv cc ) at maximum v in . when the voltage applied to extv cc rises above 4.7v , the v bias ldo is turned off and the extv cc ldo is enabled. the extv cc ldo remains on as long as the voltage applied to extv cc remains above 4.5v . the extv cc ldo attempts to regulate the intv cc voltage to 5.4v , so while extv cc is less than 5.4v , the ldo is in dropout and the intv cc voltage is approximately equal to extv cc . when extv cc is greater than 5.4v , up to an absolute maximum of 14v, intv cc is regulated to 5.4v. using the extv cc ldo allows the mosfet driver and control power to be derived from one of the ltc3859as switching regulator outputs ( 4.7v v out 14v ) dur - ing normal operation and from the v bias ldo when the output is out of regulation (e.g., startup, short-circuit). if more current is required through the extv cc ldo than is specified, an external schottky diode can be added between the extv cc and intv cc pins. in this case, do not apply more than 6v to the extv cc pin and make sure that extv cc v bias . significant efficiency and thermal gains can be realized by powering intv cc from the buck output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). for 5v to 14v regulator outputs, this means connecting the extv cc pin directly to v out . tying the extv cc pin to a 8.5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (40ma)(8.5v)(34c/w) = 82c however, for 3.3v and other low voltage outputs, additional circuitry is required to derive intv cc power from the output. downloaded from: http:///
ltc3859a 28 3859afa applications information the following list summarizes the four possible connec - tions for extv cc : 1. extv cc grounded. this will cause intv cc to be powered from the internal 5.4v regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to the output voltage of one of the buck regulators. this is the normal connection for a 5v to 14v regulator and provides the highest ef - ficiency. 3. extv cc connected to an external supply. if an external supply is available in the 5v to 14v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. ensure that extv cc < v bias . 4. extv cc connected to an output-derived boost network off one of the buck regulators. for 3.3v and other low voltage buck regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v . this can be done with the capacitive charge pump shown in figure 9. ensure that extv cc < v bias . figure 9. capacitive charge pump for extv cc 3859a f09 ltc3859a tg sw bg pgnd r sense mtopmbot l extv cc bat85 bat85 c1 v in1,2 bat85 v out1,2 downloaded from: http:///
ltc3859a 29 3859afa applications information topside mosfet driver supply (c b , d b ) external bootstrap capacitors c b connected to the boost pins supply the gate drive voltages for the topside mos - fets. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate-source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in for the buck channels (v out for the boost channel) and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply : v boost = v in + v intvcc (v boost = v out + v intvcc for the boost controller). the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) for the buck channels and v out(max) for the boost channel. the external diode d b can be a schottky diode or silicon diode, but in either case it should have low leakage and fast recovery. pay close attention to the reverse leakage at high temperatures where it generally increases substantially. the topside mosfet driver for the boost channel includes an internal charge pump that delivers current to the bootstrap capacitor from the boost3 pin. this charge current maintains the bias voltage required to keep the top mosfet on continuously during dropout/overvolt - age conditions. the schottky/silicon diode selected for the boost topside driver should have a reverse leakage less than the available output current the charge pump can supply. curves displaying the available charge pump current under different operating conditions can be found in the typical performance characteristics section. a leaky diode d b in the boost converter can not only prevent the top mosfet from fully turning on but it can also completely discharge the bootstrap capacitor c b and create a current path from the input voltage to the boost3 pin to intv cc . this can cause intv cc to rise if the diode leakage exceeds the current consumption on intv cc . this is particularly a concern in burst mode operation where the load on intv cc can be very small. there is an internal voltage clamp on intv cc that prevents the intv cc voltage from running away, but this clamp should be regarded as a failsafe only. the external schottky or silicon diode should be carefully chosen such that intv cc never gets charged up much higher than its normal regulation voltage.care should also be taken when choosing the external diode d b for the buck converters. a leaky diode not only increases the quiescent current of the buck converter, but it can also cause a similar leakage path to intv cc from v out for applications with output voltages greater than the intv cc voltage (~5.4v). figure 10. relationship between oscillator frequency and resistor value at the freq pin freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 3859a f10 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125 downloaded from: http:///
ltc3859a 30 3859afa applications information fault conditions: buck current limit and current foldback the ltc3859 a includes current foldback for the buck channels to help limit load current when the output is shorted to ground. if the buck output falls below 70% of its nominal output level, then the maximum sense volt - age is progressively lowered from 100% to 40% of its maximum selected value. under short-circuit conditions with very low duty cycles, the buck channel will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short-circuit ripple current is determined by the minimum on-time t on(min) of the ltc3859 a ( 95ns ), the input volt - age and inductor value: d i l(sc) = t on(min) (v in /l) the resulting average short-circuit current is: i sc = 40% ? i lim(max) ? 1 2 d i l(sc) fault conditions: buck overvoltage protection (crowbar) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the one of the buck regulators rises much higher than nominal levels. the crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top mosfet if the short oc - curs while the controller is operating. a comparator monitors the buck output for overvoltage conditions. the comparator detects faults greater than 10% above the nominal output voltage. when this condi - tion is sensed, the top mosfet of the buck controller is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. the bottom mosfet remains on continuously for as long as the over voltage condition persists ; if v out returns to a safe level, normal operation automatically resumes. a shorted top mosfet for the buck channel will result in a high current condition which will open the system fuse. the switching regulator will regulate properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. fault conditions: over temperature protection at higher temperatures, or in cases where the internal power dissipation causes excessive self heating on chip (such as intv cc short to ground), the over temperature shutdown circuitry will shut down the ltc3859 a. when the junction temperature exceeds approximately 170c, the over temperature circuitry disables the intv cc ldo, causing the intv cc supply to collapse and effectively shutting down the entire ltc3859 a chip. once the junc - tion temperature drops back to approximately 155c , the int v cc ldo turns back on. long term overstress (t j > 125c ) should be avoided as it can degrade the perfor - mance or shorten the life of the part.phase-locked loop and frequency synchronization the lt c3859 a has an internal phase-locked loop (pll) comprised of a phase frequency detector, a lowpass filter, and a voltage-controlled oscillator (vco). this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the pllin/mode pin. the turn-on of controller 2 s top mosfet is thus 180 degrees out of phase with the external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. if the external clock frequency is greater than the internal oscillator s frequency, f osc , then current is sourced continu - ously from the phase detector output, pulling up the vco input. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the vco input. downloaded from: http:///
ltc3859a 31 3859afa applications information if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage at the vco input is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the internal filter capacitor, clp, holds the voltage at the vco input. note that the ltc3859 a can only be synchronized to an external clock whose frequency is within range of the ltc3859a s internal vco, which is nominally 55khz to 1mhz . this is guaranteed to be between 75khz and 850khz . typically, the external clock (on pllin/mode pin) input high threshold is 1.6v , while the input low threshold is 1.2v . rapid phase-locking can be achieved by using the freq pin to set a free-running frequency near the desired synchro - nization frequency. the vco s input voltage is prebiased at a frequency correspond to the frequency set by the freq pin. once prebiased, the pll only needs to adjust the frequency slightly to achieve phase-lock and synchro - nization. although it is not required that the free-running frequency be near external clock frequency , doing so will prevent the operating frequency from passing through a large range of frequencies as the pll locks. t able 1 summarizes the different states in which the freq pin can be used. table 1 freq pin pllin/mode pin frequency 0v dc voltage 350khz intv cc dc voltage 535khz resistor to sgnd dc voltage 50khz to 900khz any of the above external clock phase-locked to external clock minimum on-time considerations minimum on-time t on(min) is the smallest time duration that the ltc3859 a is capable of turning on the top mosfet (bottom mosfet for the boost controller). it is det ermined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that t on(min)_ buck < v out v in (f) t on(min)_ boost < v out ? v in v out (f) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc3859 a is approximately 95ns for the bucks and 120ns for the boost. however, as the peak sense voltage decreases the minimum on-time gradually increases up to about 130ns . this is of particu - lar concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. downloaded from: http:///
ltc3859a 32 3859afa applications information efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3859 a circuits : 1) ic v bias current, 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v bias current is the dc supply current given in the electrical characteristics table, which excludes mos - fet driver and control currents. v bias current typically results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge, dq, moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc from an output-derived source power through extv cc will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/ (efficiency). for example, in a 20v to 5v application, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resis - tor, and input and output capacitor esr. in continuous mode the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resis - tances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 30m , r l = 50m , r sense = 10m and r esr = 40m (sum of both input and output capacitance losses), then the total resistance is 130m . this results in losses ranging from 3% to 13% as the output current increases from 1a to 5a for a 5v output, or a 4% to 20% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the top mosfet(s) (bot - tom mosfet for the boost), and become significant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: transition loss = (1.7)v in 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. the ltc3859a 2- phase architecture typically halves this input capacitance requirement over competing solu - tions. other losses including schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. downloaded from: http:///
ltc3859a 33 3859afa applications information checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to d i load(esr) , where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti- loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the i th pin not only allows optimization of control loop behavior, but it also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response. assuming a predominantly second order system, phase margin and/ or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in figure 16 will provide an adequate starting point for most applications. the i th series rc-cc filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output ca - pacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing rc and the bandwidth of the loop will be increased by de - creasing cc. if rc is increased by the same factor that cc is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply per formance. a second, more severe transient is caused by switching in loads with large ( >1f ) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1 : 50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma.buck design example as a design example for one of the buck channels channel, assume v in = 12v (nominal) , v in = 22v (max) , v out = 3.3v, i max = 6a, v sense(max) = 50mv, and f = 350khz. the inductance value is chosen first based on a 30% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. tie the freq pin to gnd, generating 350khz operation. the minimum inductance for 30% ripple current is: d i l = v out (f)(l) 1 ? v out v in(nominal) ?? ?? ?? ?? a 3.9h inductor will produce 29% ripple current. the peak inductor current will be the maximum dc value plus one half the ripple current, or 6.88a . increasing the ripple current will also help ensure that the minimum on-time downloaded from: http:///
ltc3859a 34 3859afa applications information of 95ns is not violated. the minimum on-time occurs at maximum v in : t on(min) = v out v in(max) (f) = 3.3v 22v(350khz) = 429ns the r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (43mv): r sense 43mv 6.88a = 0.006 choosing 1% resistors : r a = 25k and r b = 80.6k yields an output voltage of 3.33v. the power dissipation on the top side mosfet can be easily estimated. choosing a fairchild fd s6982 s dual mosfet results in : r ds(on) = 0.035/0.022 , c miller = 215pf. at maximum input voltage with t(estimated) = 50c: p main = 3.3v 22v (6a) 2 1 + (0.005)(50 c ? 25 c) { } (0.035 ) + (22v) 2 6 5a 2 (2.5 )(215pf) ? 1 5v ? 2.3v + 1 2.3v ?? ? ?? ? (350khz) = 433mw a short-circuit to ground will result in a folded back cur - rent of: i sc = 20 mv 0.006 ? 1 2 95ns(22v) 3.9h ?? ? ?? ? = 3.07a with a typical value of r ds(on) and z = (0.005/ c)(25c) = 0.125. the resulting power dissipated in the bottom mosfet is: p sync = (2.23a) 2 (1.125)(0.022 ) = 233mw which is less than under full-load conditions.the input capacitor to the buck regulator c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on. c out is chosen with an esr of 0.02 for low output ripple. the output ripple in continuous mode will be highest at the maximum input volt - age. the output voltage ripple due to esr is approximately : v oripple = r esr ( d i l ) = 0.02(1.75a) = 35mv p-p pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 11. figure 12 illustrates the current waveforms present in the various branches of the 2-phase synchronous buck regulators operating in the continuous mode. check the following in your layout: 1. are the top n-channel mosfets mto p1 and mto p2 located within 1cm of each other with a common drain connection at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate ? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out ( C ) ter - minals. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor ( C) terminals should be connected as close as possible to the ( C ) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. do the ltc3859 a v fb pins resistive dividers connect to the (+) terminals of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. are the sense C and sense + leads routed together with minimum pc trace spacing ? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers cur - rent peaks. an additional 1f ceramic capacitor placed immediately next to the int v cc and pgnd pins can help improve noise performance substantially. downloaded from: http:///
ltc3859a 35 3859afa 6. keep the switching nodes (sw1, sw2, sw3), top gate nodes (t g1 , t g2 , t g3 ), and boost nodes (boost1, boost2, boost3) away from sensitive small-signal nodes, especially from the opposites channel s voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3859 a and occupy minimum pc trace area. 7. use a modified star ground technique : a low impedance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. pc board layout debugging start with one controller on at a time. it is helpful to use a dc- 50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switch - ing node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper per formance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold typically 25% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug - gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un - dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation.investigate whether any problems exist only at higher out - put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. an embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistor don t worry, the regulator will still maintain control of the output voltage. applications information downloaded from: http:///
ltc3859a 36 3859afa applications information figure 11. branch current waveforms for bucks r l1 d1 l1 sw1 r sense1 v out1 c out1 v in c in r in r l2 d2 bold lines indicatehigh switching current. keep lines to a minimum length. l2 sw2 3859a f11 r sense2 v out2 c out2 downloaded from: http:///
ltc3859a 37 3859afa typical applications figure 12. high efficiency wide input range dual 5v/8.5v converter 3859a f12 ltc3859a sense1 C sense1 + pgood1 tg1 sw1 boost1 bg1 v bias pgnd intv cc tg2 boost2 sw2 bg2 sense2 + sense2 C tg3 sw3 boost3 bg3 sense3 C sense3 + v fb1 i th1 track/ss1freq pllin/mode sgnd run1 run2 run3 v fb2 i th2 track/ss2v fb3 i th3 ss3 c11nf 100k c b1 0.1f d1 d2 c bias 10f c int1 4.7f c21nf mtop1 mbot1 c110f l1 4.9h r sense1 6m c out1 220f v out1 5v5a mtop2 mbot2 c210f l2 6.5h r sense2 8m c out2 68f v out2 8.5v 3a c b2 0.1f mtop3 mbot3 l3 1.2h r sense2 2m c31nf d3 c b3 0.1f c in 220f v in 2.5v to 38v (start-up above 5v) * v out3 is 10v when v in < 10v, follows v in when v in > 10v c out3 220f r b1 357k opt v out1 r a1 68.1k r b2 649k 10pf v out2 r a2 68.1k c ith1a 100pf c ith1 1500pf r ith1 15k c ith2a 68pf c ith2 2.2nf c ss2 0.1f r ith2 15k r b3 499k opt v out3 r a3 68.1k c ith3a 820pf c ith3 0.01f c ss3 0.1f r ith3 3.6k c ss1 0.1f mtop1, mtop2: bsz097no4lsmbot1, mbot2: bsz097no4ls mtop3: bsc027no4ls mbot3: bsco1bn04ls l1: wrth 744314490 l2: wrth 744314650 l3: wrth 744325120 c out1 : sanyo 6tpb220ml c out2 : sanyo 10tpc68m c in , c out3 : sanyo 50ce220lx d1, d2: cmdh-4ed3: bas140w v out3 10v* ov3 extv cc v out1 downloaded from: http:///
ltc3859a 38 3859afa typical applications figure 13. high efficiency wide input range dual 12v/3.3v converter 3859a f13 ltc3859a sense1 C sense1 + pgood1 tg1 sw1 boost1 bg1 v bias pgnd intv cc tg2 boost2 sw2 bg2 sense2 + sense2 C tg3 sw3 boost3 bg3 sense3 C sense3 + v fb1 i th1 track/ss1freq pllin/mode sgnd run1 run2 run3 v fb2 i th2 track/ss2v fb3 i th3 ss3 c11nf 100k c b1 0.1f d1 d2 c bias 10f c int1 4.7f c21nf mtop1 mbot1 c110f l1 8.8h r sense1 9m c out1 47f v out1 12v 3a mtop2 mbot2 c210f l2 3.2h r sense2 6m c out2 150f v out2 3.3v 5a c b2 0.1f mtop3 mbot3 l3 1.2h r sense2 2m c31nf d3 c b3 0.1f c in 220f v in 2.5v to 38v (start-up above 5v) * v out3 is 15v when v in < 15v, follows v in when v in > 15v c out3 220f r b1 475k 33pf v out1 r a1 34k r b2 215k 15pf v out2 r a2 68.1k c ith1a 100pf c ith1 680pf r ith1 10k c ith2a 150pf c ith2 820pf c ss2 0.1f r ith2 15k r b3 787k opt v out3 r a3 68.1k c ith3a 820pf intv cc c ith3 0.01f c ss3 0.1f r ith3 3.6k c ss1 0.1f mtop1, mtop2: vishay si7848dp mbot1, mbot2: vishay si7848dp mtop3: bsc027no4ls mbot3: bsco1bn04ls l1: sumida cdep105-8r8m l2: sumida cdep105-3r2m l3: wrth 744325120 c out1 : kemet t525d476mo16e035 c out2 : sanyo 4tpe150m c in , c out3 : sanyo 50ce220lx d1, d2: cmdh-4ed3: bas140w v out3 15v* ov3 100k extv cc downloaded from: http:///
ltc3859a 39 3859afa typical applications figure 14. high efficiency triple 24v/1v/1.2v converter from 12v v in 3859a f14 ltc3859a sense1 C sense1 + pgood1 tg1 sw1 boost1 bg1 v bias pgnd intv cc tg2 boost2 sw2 bg2 sense2 + sense2 C tg3 sw3 boost3 bg3 sense3 C sense3 + v fb1 i th1 track/ss1freq pllin/mode sgnd run1 run2 run3 v fb2 i th2 track/ss2v fb3 i th3 ss3 c11nf 100k c b1 0.1f d1 d2 c bias 10f c int1 4.7f c21nf mtop1 mbot1 c110f l1 0.47h r sense1 3.5m c out1 220f 2 v out1 1v8a mtop2 mbot2 c210f l2 0.47h r sense2 3.5m c out2 220f 2 v out2 1.2v8a c b2 0.1f mtop3 mbot3 l3 3.3h r sense2 4m c31nf d3 c b3 0.1f c in 220f c out3 220f r b1 28.7k 56pf v out1 r a1 115k r b2 57.6k 56pf v out2 r a2 115k c ith1a 200pf c ith1 1000pf r ith1 3.93k c ith2a 200pf c ith2 1000pf c ss2 0.01f r ith2 3.93k r b3 232k opt v out3 r a3 12.1k c ith3a 220pf c ith3 15nf c ss3 0.01f r ith3 8.66k c ss1 0.01f mtop1, mtop2: renesas rjk0305mbot1, mbot2: renesas rjk0328 mtop3, mbot3: renesas hat2169h l1, l2: sumida cdep105-0r4 l3: pulse pa1494.362nl c out1 , c out2 : sanyo 2r5tpe220m c in , c out3 : sanyo 50ce220ax d1, d2: cmdh-4ed3: bas140w v out3 24v5a v in 12v ov3 extv cc downloaded from: http:///
ltc3859a 40 3859afa typical applications figure 15. high efficiency 1.2v/3.3v step-down converter with 10.5v sepic converter 3859a f15 ltc3859a sense1 C sense1 + pgood1 tg1 sw1 boost1 bg1 v bias pgnd intv cc tg2 boost2 sw2 bg2 sense2 + sense2 C tg3 sw3 boost3 bg3 sense3 C sense3 + v fb1 i th1 track/ss1freq pllin/mode sgnd run1 run2 run3 v fb2 i th2 track/ss2v fb3 i th3 ss3 c11nf 100k c b1 0.1f d1 d2 c bias 10f c int1 4.7f c21nf mtop1 mbot1 c110f l1 2.2h r sense1 9m c out1 220f v out1 1.2v3a mtop2 mbot2 c210f l2 6.5h r sense2 9m c out2 220f v out2 3.3v3a c b2 0.1f mbot3 l3 10h d3 r sense2 9m c31nf c310f 50v c in 220f c out3 270f r b1 57.6k v out1 r a1 115k r b2 357k v out2 r a2 115k c ith1a 100pf c ith1 2.2nf r ith1 5.6k c ith2a 100pf c ith2 3.3nf c ss2 0.1f r ith2 9.1k r b3 887k v out3 r a3 115k c ith3a 10pf c ith3 100nf c ss3 0.1f r ith3 13k c ss1 0.1f mtop1, mtop2: bsz097no4lsmbot1, mbot2: bsz097no4ls mbot3: bsz097no4l l1: wurth 744311220 l2: wurth 744314650 l3: cooper bussmann drq125-100 c out1 : sanyo 2r5tpe220mafb c out2 : sanyo 4tpe220mazb c out3 : sanyo svpc270m c in : sanyo 50ce220lx d1, d2: cmdh-4ed3: diodes inc b360a-13-f v out3 10.5v1.2a v in 5.8v to 34v ? ? ov3 extv cc downloaded from: http:///
ltc3859a 41 3859afa package description fe package 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1772 rev c) exposed pad variation aa 4.75 (.187) ref fe38 (aa) tssop rev c 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 19 20 ref 9.60 ? 9.80* (.378 ? .386) 38 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.50 (.0196) bsc 0.17 ? 0.27 (.0067 ? .0106) typ recommended solder pad layout 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc please refer to http://www.linear.com/product/ltc3859a#packaging for the most recent package drawings. downloaded from: http:///
ltc3859a 42 3859afa package description uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1top mark (see note 6) 37 12 38 bottom viewexposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 C 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 packageoutline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notchr = 0.30 typ or 0.35 45 chamfer please refer to http://www.linear.com/product/ltc3859a#packaging for the most recent package drawings. downloaded from: http:///
ltc3859a 43 3859afa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 06/16 block diagram clarification corrected pmain_boost equationmodified points #3 and #4 modified figure 9 13, 14 2328 28 downloaded from: http:///
ltc3859a 44 3859afa ? linear technology corporation 2011 lt 0616 rev a ? printed in usa related parts part number description comments ltc3857/ltc3857-1 ltc3858/ltc3858-1 low i q , dual output 2-phase synchronous step-down dc/ dc controllers with 99% duty cycle phase-lockable fixed frequency 50khz to 900khz, 4v v in 38v, 0.8v v out 24v, i q = 50a/170a ltc3890/ltc3890-1 60v, low i q , dual 2-phase synchronous step-down dc/ dc controller phase-lockable fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3789 4-switch high efficiency buck-boost controller 4v v in 38v, 0.8v v out 38v, ssop-28, 4mm 5mm qfn-28 ltc3834/ltc3834-1 ltc3835/ltc3835-1 low i q , synchronous step-down dc/dc controller with 99% duty cycle phase-lockable fixed frequency 140khz to 650khz, 4v v in 36v, 0.8v v out 10v, i q = 30a/80a ltc3891 60v, low i q , synchronous step-down dc/dc controller with 99% duty cycle pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, tssop-20e, 3mm 4mm qfn-20 ltc3824 low i q , high voltage dc/dc controller, 100% duty cycle selectable fixed 200khz to 600khz operating frequency, 4v v in 60v, 0.8v v out v in , i q = 40a, msop-10e typical application high efficiency wide input range dual 3.3v/8.5v converter 3859a ta02 ltc3859a sense1 C sense1 + pgood1 tg1 sw1 boost1 bg1 v bias pgnd intv cc tg2 boost2 sw2 bg2 sense2 + sense2 C tg3 sw3 boost3 bg3 sense3 C sense3 + v fb1 i th1 track/ss1freq pllin/mode sgnd run1 run2 run3 v fb2 i th2 track/ss2v fb3 i th3 ss3 c11nf 100k c b1 0.1f d1 d2 c bias 10f c int1 4.7f c21nf mtop1 mbot1 c110f l1 3.2h r sense1 6m c out1 150f v out1 3.3v5a mtop2 mbot2 c210f l2 6.5h r sense2 8m c out2 68f v out2 8.5v 3a c b2 0.1f mtop3 mbot3 l3 1.2h r sense2 2m c31nf d3 c b3 0.1f c in 220f v in 2.5v to 38v (start-up above 5v) * v out3 is 10v when v in < 10v, follows v in when v in > 10v c out3 220f r b1 215k 15pf v out1 r a1 68.1k r b2 649k 10pf v out2 r a2 68.1k c ith1a 150pf c ith1 820pf r ith1 15k c ith2a 68pf c ith2 2.2nf c ss2 0.1f r ith2 15k r b3 499k opt v out3 v out2 r a3 68.1k c ith3a 820pf c ith3 0.01f c ss3 0.1f r ith3 3.6k c ss1 0.1f mtop1, mtop2: vishay si7848dp mbot1, mbot2: bsz097no4ls mtop3: bsc027no4ls mbot3: bsco1bn04ls l1: sumida cdep105-3r2m l2: wrth 744314650 l3: wrth 744325120 c out1 : sanyo 6tpb220ml c out2 : sanyo 4tpe150m c in , c out3 : sanyo 50ce220lx d1, d2: cmdh-4ed3: bas140w v out3 10v* ov3 extv cc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3859a downloaded from: http:///

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